Although nonvolatile semiconductor storage units of various schemes have now been put into practical use, a flash EEPROM (flash electrically erasable and programmable read only memory) that electrically executes flash erase is still the mainstream. Several kinds of cell structures have been released in association with the flash EEPROM. A stacked cell is generally used, in which a control gate electrode is stacked on a floating gate, as described in reference 1 (“Dictionary of Semiconductor Terms” supervised by Junichi Nishizawa, Nikkan Kogyo Shimbun, Mar. 20, 1999, pp. 970-972). FIG. 37A shows the structure. As shown in FIG. 37A, in the conventional cell structure, diffusion layers 202 serving as source and drain regions are formed in the surface region of a p-type silicon substrate 201. A gate insulating film 203 made of a silicon oxide film is formed on the substrate, and a floating gate 204 is stacked on the gate insulating film 203. An inter-gate insulating film 205 having, e.g., an ONO (silicon oxide film/silicon nitride film/silicon oxide film) structure is formed on the floating gate 204. A control gate electrode 206 is stacked on the inter-gate insulating film 205.
The erase and write for the memory cell are executed in the following way. In the erase, as shown in FIG. 37B, the control gate electrode is grounded, and the drain floats. A voltage of 12 V is applied to the source to apply a high electric field to the gate insulating film 203 so that electrons accumulated in the floating gate 204 are removed to the source by the FN (Fowler-Nordheim) current. In the write, a ground potential and a voltage of 5 V are applied to the source and drain, respectively. A voltage of 12 V is applied to the control gate electrode 206 to generate CHE (Channel Hot Electrons) in the channel, and some of them are injected into the floating gate.